1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device. More particularly, the present invention relates to a fabrication method for a salicide gate.
2. Description of the Related Art
There is a continuing effort in the semiconductor industry to increase the integration density on a semiconductor device, for example, by reducing the device dimension. As a result, the gate resistance is increased, leading to an increase of the gate response time. Currently, the common approach to reduce the gate response time and to increase the operational speed of a device is to form a salicide layer on the polysilicon gate. A polysilicon gate with a salicide layer formed thereon is known as a salicide gate. FIG. 1A to 1C are cross-sectional views showing the processing of a salicide gate according to the prior art.
As shown in FIG. 1A, a gate oxide layer 110 and a polysilicon gate 120 is formed on a substrate 100. Spacers 130 are further formed on the sidewalls of the gate oxide layer 110 and the polysilicon gate 120. An ion implantation is then conducted to form a pair of source/drain regions 140 in the substrate 100 on both sides of the spacers 130. After this, a metal layer 150 is deposited on the substrate 100.
Continuing to FIG. 1B, a thermal process is conducted to induce a reaction between the metal layer 150 and the source/drain regions 140 and the polysilicon gate 120, respectively, to form a salicide layer 170 on the source/drain region 140 and a salicide layer 160 on the polysilicon gate 120. The unreacted metal layer 150, as shown in FIG. 1C, is removed to complete the manufacturing of a salicide gate 180.
This conventional approach in forming a salicide gate, however, has its disadvantages, especially for a dynamic random access memory (DRAM) device. Although the gate resistance is reduced in the conventional approach, a low resistance salicide layer is also formed on the source/drain regions. A higher leakage current is thus existed between the source/drain regions and the capacitor of the DRAM cell, which adversely affecting the data retention characteristics of the DRAM cell. The DRAM cell must therefore be refreshed frequently and the operational efficiency of the device is thereby reduced.